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16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information FEATURES: * Organized as 1M x16 * Dual-Bank Architecture for Concurrent Read/Write Operation - 16 Mbit Bottom Sector Protection - SST36VF1601: 12 Mbit + 4 Mbit - 16 Mbit Top Sector Protection - SST36VF1602: 4 Mbit + 12 Mbit * Single 2.7-3.6V Read and Write Operations * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 25 mA (typical) - Standby Current: 4 A (typical) - Auto Low Power Mode: 4 A (typical) * Hardware Sector Protection/WP# Input Pin - Protects 4 outer most sectors (4 KWord) in the larger bank by driving WP# low and unprotects by driving WP# high * Hardware Reset Pin (RESET#) - Resets the internal state machine to reading data array * Sector-Erase Capability - Uniform 1 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks PRODUCT DESCRIPTION The SST36VF1601/1602 are 1M x16 CMOS Concurrent Read/Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.The SST36VF1601/ 1602 write (Program or Erase) with a 2.7-3.6V power supply. The SST36VF1601/1602 devices conform to JEDEC standard pinouts for x16 memories. Featuring high performance Word-Program, the SST36VF1601/1602 devices provide a typical Word-Program time of 14 sec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST36VF1601/1602 devices have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST36VF1601/1602 devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. * Read Access Time - 70 and 90 ns * Latched Address and Data * Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 70 ms (typical) - Word-Program Time: 14 s (typical) - Chip Rewrite Time: 8 seconds (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bit - Data# Polling - Ready/Busy# pin * CMOS I/O Compatibility * Conforms to Common Flash Memory Interface (CFI) * JEDEC Standards - Flash EEPROM Pinouts and command sets * Packages Available - 48-Pin TSOP (12mm x 20mm) - 48-Ball TFBGA (8mm x 10mm)
1 2 3 4 5 6 7 8 9 10
The SST36VF1601/1602 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST36VF1601/1602 significantly improve performance and reliability, while lowering power consumption. The SST36VF1601/1602 inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST36VF1601/1602 also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technolo-
11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. Concurrent SuperFlash is a trademark of Silicon Storage Technology, Inc. 373-3 11/00 S71142 These specifications are subject to change without notice. 1
16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information gies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST36VF1601/1602 are offered in 48-pin TSOP and 48ball TFBGA packages. See Figures 3 and 4 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST36VF1601/1602 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current to typically 4 A. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. Concurrent Read/Write Operation Dual bank architecture of SST36VF1601/1602 devices allows the Concurrent Read/Write operation whereby the user can read from one bank while program or erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. CONCURRENT READ/WRITE STATE TABLE Bank 1 Read Read Write Write No Operation No Operation Bank 2 No Operation Write Read No Operation Read Write in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 5). Word-Program Operation The SST36VF1601/1602 are programmed on a word-byword basis. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams and Figure 19 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Sector- (Block-) Erase Operation The Sector- (Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-by-block) basis. The SST36VF1601/1602 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-Erase Operation The SST36VF1601/1602 provide a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the "1" state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or
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Note: For the purposes of this table, write means to Block-, Sector-, or Chip-Erase, or Word-Program as applicable to the appropriate bank.
Read The Read operation of the SST36VF1601/1602 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is
(c) 2000 Silicon Storage Technology, Inc.
16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bits or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 22 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SST36VF1601/1602 provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The hadware detection uses the Ready/Busy# (RY/BY#) output pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), a Data# Polling (DQ7) or Toggle Bit (DQ6) read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Ready/Busy# (RY/BY#) The SST36VF1601/1602 includes a Ready/Busy# (RY/ BY#) output signal. During any SDP initiated operation, e.g., Erase, Program, CFI or ID Read operation, RY/BY# is actively pulled low, indicating a SDP controlled operation is in Progress. The status of RY/BY# is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Bank-Erase, the RY/BY# is valid after the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull up resistor. Ready/Busy# is in high impedance whenever OE# or CE# is high or RST# is low. Data# Polling (DQ7) When the SST36VF1601/1602 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a `1'. The Data# Polling (DQ7) is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling (DQ7) is valid after
(c) 2000 Silicon Storage Technology, Inc.
the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling (DQ7) timing diagram and Figure 20 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1's and 0's, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit (DQ6) is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 21 for a flowchart. Data Protection The SST36VF1601/1602 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Hardware Block Protection The SST36VF1601/1602 provide a hardware block protection which protects the outermost 4 KWords in the larger bank.The block is protected when WP# is held low. See Figures 1 and 2 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire write operation has completed. Hardware Reset (RESET#) When the RESET# input pin is held low for at least TRP, any in progress operation will terminate and return to Read mode. If the part is not busy, a minimum period of TRHR is required after RESET# is driven high before a valid read can take place. If the part is busy, poll RY/BY#, Data# Polling, or Toggle Bit to determine when the device is ready. Initiating a reset during a Write operation (Program or Erase) is not recommended. Data may be in an undetermined state.
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information Software Data Protection (SDP) The SST36VF1601/1602 provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST36VF1601/ 1602 are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 are "Don't Care" during any SDP command sequence. Common Flash Memory Interface (CFI) The SST36VF1601/1602 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address 555H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the devices and manufacturer. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram and Figure 21 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION WORD Manufacturers ID Device ID SST36VF1601 Device ID SST36VF1602 0000 H 0001 H 0001 H DATA 00BF H 2761 H 2762 H
373 PGM T1.0
Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 15 for timing waveform and Figure 21 for a flowchart.
FUNCTIONAL BLOCK DIAGRAM
Memory Address Address Buffers (4 KWord Sector Protection) SuperFlash Memory 12 Mbit Bank RESET# CE# WP# WE# OE# RY/BY#
373 ILL B37.4
SuperFlash Memory 4 Mbit Bank Control Logic I/O Buffers DQ15 - DQ0
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
Bottom Sector Protection; 32 KWord Blocks; 1 KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block 31 Block 30 Block 29
1 2
Bank 2 Bank 1
Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22 Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1
3 4 5 6 7 8 9 10 11 12 13 14 15
4 KWord Sector Protection (4- 1 KWord Sectors)
Block 0
373 ILL F38.2
16
FIGURE 1: SST36VF1601, 1 MEGABIT X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
Top Sector Protection; 32 KWord Blocks; 1 KWord Sectors
4 KWord Sector Protection (4- 1 KWord Sectors)
FFFFFH FF000H FEFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 00FFFFH 000000H Block 31
Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Block 22
Bank 2 Bank 1
373 ILL F39.2
Block 21 Block 20 Block 19 Block 18 Block 17 Block 16 Block 15 Block 14 Block 13 Block 12 Block 11 Block 10 Block 9 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0
FIGURE 2: SST36VF1602, 1 MEGABIT X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Standard Pinout Top View Die Up
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8
373 ILL F01b.2
FIGURE 3: PIN ASSIGNMENTS FOR 48-PIN TSOP (12MM X 20MM)
TOP VIEW (balls facing down)
9 10
6 5 4 3 2
A13 A9
A12 A8
A14 A10
A15 A11 A19 NC A5 A1
A16
NC
DQ15 VSS
DQ7 DQ14 DQ13 DQ6 DQ5 DQ12 VDD DQ4 DQ2 DQ10 DQ11 DQ3 DQ0 DQ8 A0 CE# DQ9 DQ1 OE# VSS
WE# RESET# NC RY/BY# WP# A18 A7 A17 A4 A6 A2
11 12 13
1
A3
A
B
C
D
E
F
G
H
373 ILL F01a.4
SST36VF1601/1602
14 15 16
FIGURE 4: PIN ASSIGNMENTS FOR 48-BALL TFBGA (8MM X 10MM)
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information TABLE 2: PIN DESCRIPTION Symbol Pin Name A19-A0 Address Inputs Functions To provide memory addresses. During Sector-Erase and Hardware Sector Protection A19-A11 address lines will select the sector. During Block-Erase A19-A15 address lines will select the block. To output data during read cycles and receive input data during write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To reset and return the device to Read mode. To output the status of a Program or Erase operation. RY/BY# is an open drain output, so a 10KW - 100KW pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. To protect and unprotect top or bottom 4 sectors from Erase or Program operation. To provide 2.7-3.6V power supply voltage Unconnected pins.
373 PGM T2.3
DQ15-DQ0
Data Input/output
CE# OE# WE# RESET# RY/BY#
Chip Enable Output Enable Write Enable Reset Ready/Busy#
WP# VDD Vss NC
Write Protect Power Supply Ground No Connection
TABLE 3: OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification
CE# VIL VIL VIL VIH X X
OE# VIL VIH VIH X VIL X
WE# VIH VIL VIL X X VIH
DQ DOUT DIN X High Z High Z/ DOUT High Z/ DOUT
Address AIN AIN Sector or block address, XXH for Chip-Erase X X X A19 - A1 = VIL, A0 = VIL A19 - A1 = VIL, A0 = VIH See Table 4
373 PGM T3a.4
Software Mode
VIL
VIL
VIH
Manufacturer ID (00BF) Device ID1
Note 1. Device ID = 2761H for SST36VF1601 and 2762H for SST36VF1602
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information TABLE 4: SOFTWARE COMMAND SEQUENCE
Command Sequence 1st Bus Write Cycle Addr1 Data5 2nd Bus Write Cycle Addr1 Data5 3rd Bus Write Cycle Addr1 Data5 4th Bus Write Cycle Addr1 Data5 5th Bus Write Cycle Addr1 Data5 6th Bus Write Cycle Addr1 Data5 SAx2 30H BAx2 50H 5555H 10H
1 2 3 4
Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Data Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H Software ID Entry6,7 5555H AAH 2AAAH 55H 5555H 90H CFI Query Entry 5555H AAH 2AAAH 55H 5555H 98H Software ID Exit/ XXH F0H CFI Exit4 Software ID Exit/ 5555H AAH 2AAAH 55H 5555H F0H CFI Exit4 Notes: 1. Address format A14-A0 (Hex), Address A15-A19 are "Don't Care" for Command sequence for SST36VF1601/1602 2. SAx for Sector-Erase; uses A19-A11 address lines BAx, for Block-Erase; uses A19-A15 address lines 3. WA = Program word address 4. Both Software ID Exit/CFI Exit operations are equivalent 5. DQ15 - DQ8 are "Don't Care" for Command sequence SST Manufacturer ID = 00BFH, is read with A0 = 0, 6. With A19 -A1 =0; SST36VF1601 Device ID = 2761H, is read with A0 = 1. SST36VF1602 Device ID = 2762H, is read with A0 = 1. 7. The device does not remain in Software Product Identification Mode if powered down.
373 PGM T4.2
5 6 7 8 9 10 11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information TABLE 5: CFI QUERY IDENTIFICATION STRING1 Address Data Data 10H 0051H 11H 0052H Query Unique ASCII string "QRY" 12H 0059H 13H 0001H Primary OEM command set 14H 0007H 15H 0000H Address for Primary Extended Table 16H 0000H 17H 0000H Alternate OEM command set (00H = none exists) 18H 0000H 19H 0000H Address for Alternate OEM extended Table (00H = none exits) 1AH 0000H
Note 1: Refer to CFI publication 100 for more details.
373 PGM T5.0
TABLE 6: SYSTEM INTERFACE INFORMATION Address Data Data 1BH 0027H VDD Min. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1CH 0036H VDD Max. (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1DH 0000H VPP min. (00H = no VPP pin) 1EH 0000H VPP max. (00H = no VPP pin) 1FH 0004H Typical time out for Word-Program 2N s (24 = 16 s) 20H 0000H Typical time out for min. size buffer program 2N s (00H = not supported) 21H 0004H Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) 22H 0006H Typical time out for Chip-Erase 2N ms (26 = 64 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 24 = 32 s) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
373 PGM T6.0
TABLE 7: DEVICE GEOMETRY INFORMATION Address Data Data 27H 0015H Device size = 2N Byte (15H = 21; 221 = 2M Bytes) 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2BH 0000H 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0003H y = 1023 + 1 = 1024 sectors (03FFH = 1023) 2FH 0008H 30H 0000H z = 8 x 256 Bytes = 2 KBytes/sector (0008H = 8) 31H 001FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y = 31 + 1 = 32 blocks (001FH = 31) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
373 PGM T7.3 (c) 2000 Silicon Storage Technology, Inc. S71142 373-3 11/00
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................... -55C to +125C Storage Temperature ........................................................................................................................ -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta = 25C) ............................................................................................ 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) .................................................................................. 240C Output Short Circuit Current ............................................................................................................................. 50 mA
1 2 3 4 5
OPERATING RANGE Range Ambient Temp Commercial 0 C to +70 C Extended -20 C to +85 C
AC CONDITIONS OF TEST VDD 2.7-3.6V 2.7-3.6V Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 30 pF See Figures 16 and 17
6 7
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V Limits Symbol Parameter Min Max IDD Power Supply Current Read Program and Erase Concurrent Standby VDD Current Auto Low Power Current Reset VDD Current Input Leakage Current Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage 35 40 75 20 20 20 1 1 0.8 0.3 0.7 VDD VDD-0.3 0.2 VDD-0.2
8
Units mA mA mA A A A A A V V V V V V Test Conditions CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min. CE#=WE#=VIL, OE#=VIH, VDD=VDD Max. CE#=VIHC, VDD = VDD Max. CE#=VILC, VDD = VDD Max., all inputs = VIHC or VILC, WE# = VIHC RESET# = VSS 0.3V VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. VDD = VDD Max. IOL = 100 A, VDD = VDD Min. IOH = -100 A, VDD = VDD Min.
373 PGM T8.2
9 10 11 12 13 14 15 16
I SB I ALP IRT I LI I LO VIL VILC VIH VIHC VOL VOH
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ TPU-WRITE Power-up to Read Operation Power-up to Write Operation Minimum 100 100 Units s s
373 PGM T9.1
TABLE 10: CAPACITANCE (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition CI/O CIN1
1
Maximum 12 pF 6 pF
373 PGM T10.0
I/O Pin Capacitance Input Capacitance
VI/O = 0V VIN = 0V
TABLE 11: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Endurance - Flash Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
Minimum Specification 10,000 100 2000 200 100 + IDD
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
373 PGM T11.0
Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
(c) 2000 Silicon Storage Technology, Inc.
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information AC CHARACTERISTICS TABLE 12: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V SST36VF1601/1602-70 Symbol Parameter Min Max TRC Read Cycle Time 70 TCE Chip Enable Access Time 70 TAA Address Access Time 70 TOE Output Enable Access Time 35 1 TCLZ CE# Low to Active Output 0 OE# Low to Active Output 0 TOLZ1 1 TCHZ CE# High to High-Z Output 20 TOHZ1 OE# High to High-Z Output 20 TOH1 Output Hold from Address Change 0 1 TRP RESET# Pulse Width 500 TRHR1 RESET# High before Read 50 1,2 TRY RESET# Pin Low to Read Mode 20
SST36VF1601/1602-90 Min Max 90 90 90 45 0 0 30 30 0 500 50 20
1
Units ns ns ns ns ns ns ns ns ns ns ns s
373 PGM T12.3
2 3 4 5 6 7 8
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH1 WE# Pulse Width High 1 TCPH CE# Pulse Width High Data Setup Time TDS TDH1 Data Hold Time 1 TIDA Software ID Access and Exit Time TSE Sector-Erase TBE Block-Erase TSCE Chip-Erase TBY1 RY/BY# Delay Time 1 TRB RY/BY# Recovery Time
Min 0 40 0 0 0 10 40 40 30 30 30 0
Max 20
150 25 25 100 90 0
Units s ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ns ns
373 PGM T13.3
9 10 11 12 13 14 15 16
Note: 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase and Program operations. This parameter does not apply to Chip-Erase.
(c) 2000 Silicon Storage Technology, Inc.
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information TIMING DIAGRAMS Address and data format are in HEX.
TRC ADDRESS A19-0
TAA
CE#
TCE
OE# VIH WE# TOLZ
TOE
TOHZ TCHZ HIGH-Z DATA VALID
373 ILL F22.0
DQ15-0
HIGH-Z
TCLZ
TOH DATA VALID
FIGURE 5: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A19-0 5555 TAH TWP WE# TAS OE# TCH CE# TCS RY/BY# DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TBY TRB TWPH TDS 2AAA 5555 ADDR TDH
373 ILL F23.3
FIGURE 6: WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS A19-0 5555 TAH TCP CE# TAS OE# TCH WE# TCS RY/BY# DQ15-0 TBY TRB TCPH TDS 2AAA 5555 ADDR TDH
1 2 3 4 5 6
XXAA SW0
XX55 SW1
XXA0 SW2
DATA WORD (ADDR/DATA)
373 ILL F24.1
7 8 9
FIGURE 7: CE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 TCE CE# TOEH OE# TOE WE# TBY RY/BY# TOES
10 11 12 13 14
DQ7
DATA
DATA#
DATA#
DATA
15
373 ILL F25.1
16
FIGURE 8: DATA# POLLING TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
ADDRESS A19-0 TCE CE# TOEH OE# TOE TOES
WE# TBY RY/BY#
DQ6
TWO READ CYCLES WITH SAME OUTPUTS
373 ILL F26.1
FIGURE 9: TOGGLE BIT TIMING DIAGRAM
SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
CE#
OE# TWP WE# TBY RY/BY#
DQ7-0
AA SW0
55 SW1
80 SW2
AA SW3
55 SW4
10 SW5
373 ILL F27.2
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13)
FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc. S71142 373-3 11/00
16
16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information
SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA BAX TBE
1 2 3
CE#
OE# TWP WE#
4 5
AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 50 SW5
373 ILL F28.2
RY/BY#
DQ7-0
6 7 8 9
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) BAX = Block Address
FIGURE 11: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA SAX
TSE
10 11 12
CE#
OE# TWP WE#
13 14
AA SW0 55 SW1 80 SW2 AA SW3 55 SW4 30 SW5
373 ILL F29.2
RY/BY#
DQ7-0
15 16
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 13) SAX = Sector Address
FIGURE 12: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information
THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2
373 ILL F30.3
TIDA
TAA 00BF
Device ID
Device ID = 2761H for SST36VF1601 and 2762H for SST36VF1602
FIGURE 13: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
CE#
OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX98 SW2
373 ILL F31.0
TIDA
TAA
FIGURE 14: CFI ENTRY AND READ
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET
1 2
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
AA
55
F0 TIDA
3 4 5
CE#
OE# TWP WE# T WHP SW0 SW1 SW2
373 ILL F32.0
6 7
FIGURE 15: SOFTWARE ID EXIT/CFI EXIT
8 9 10 11
CE#/OE# TRHR RESET# TRB TRP RY/BY#
373 ILL F21.0
12 13 14 15 16
TRY
FIGURE 16: RESET# TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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16 Megabit Concurrent SuperFlash SST36VF1601 / SST36VF1602
Advance Information
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
373 ILL F14.2
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Inputs rise and fall times (10% 90%) are < 5 ns.
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT CL
373 ILL F15.1
FIGURE 18: A TEST LOAD EXAMPLE
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
Start
1 2
Load data: AAH Address: 5555H
3 4 5
Load data: 55H Address: 2AAAH
Load data: A0H Address: 5555H
6 7 8 9 10 11
373 ILL F33.1
Load Word Address/Word Data
Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed
12 13 14 15 16
FIGURE 19: WORD-PROGRAM ALGORITHM
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
Internal Timer Program/Erase Initiated
Toggle Bit Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE, TSE or TBE
Read word
Read DQ7
Program/Erase Completed
Read same word
No
Is DQ7 = true data? Yes
No
Does DQ6 match? Yes Program/Erase Completed
Program/Erase Completed
373 ILL F34.0
FIGURE 20: WAIT OPTIONS
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
CFI Query Entry Command Sequence
Software Product ID Entry Command Sequence
Software ID Exit/CFI Exit Command Sequence
1 2
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXF0H Address: XXH
3 4
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Wait TIDA
5
Load data: XX98H Address: 5555H Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation
6 7
Wait TIDA
Wait TIDA
Wait TIDA
8
Read CFI data Read Software ID Return to normal operation
373 ILL F35.1
9 10 11
FIGURE 21: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address: SAX
Load data: XX50H Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased to FFFFH
Sector erased to FFFFH
Block erased to FFFFH
373 ILL F36.1
FIGURE 22: ERASE COMMAND SEQUENCE
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information PRODUCT ORDERING INFORMATION Device Speed Suffix1 Suffix2 SST36VF160x - XXX XX XX Package Modifier K = 48 pins Numeric = Die modifier Package Type E = TSOP (12mm x 20mm) B = TFBGA (8mm x 10mm) Temperature Range C = Commercial = 0 to 70C E = Extended = -20 to 85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns, 90 = 90 ns Bank Split 1 = 12M + 4M 2 = 4M + 12M Voltage V = 2.7-3.6V
1 2 3 4 5 6 7 8 9
SST36VF1601 Valid combinations SST36VF1601-70-4C-EK SST36VF1601-70-4C-BK SST36VF1601-90-4C-EK SST36VF1601-90-4C-BK SST36VF1601-70-4E-EK SST36VF1601-90-4E-EK SST36VF1601-70-4E-BK SST36VF1601-90-4E-BK
10 11 12 13 14 15 16
SST36VF1602 Valid combinations SST36VF1602-70-4C-EK SST36VF1602-70-4C-BK SST36VF1602-90-4C-EK SST36VF1602-90-4C-BK SST36VF1602-70-4E-EK SST36VF1602-90-4E-EK SST36VF1602-70-4E-BK SST36VF1602-90-4E-BK
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 2000 Silicon Storage Technology, Inc.
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Advance Information PACKAGING DIAGRAMS
PIN # 1 IDENTIFIER 1.05 0.95 .50 BSC
.270 .170
12.20 11.80
18.50 18.30
0.15 0.05
0.70 0.50
20.20 19.80
Note:
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm.
48.TSOP-EK-ILL.4
48-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM SST PACKAGE CODE: EK
TOP VIEW BOTTOM VIEW
10.00 0.20 5.60 0.80
6 5 4 3 2 1
0.80 ABCDEFGH A1 CORNER HGFEDCBA 8.00 0.20 4.00
6 5 4 3 2 1
0.30 0.05 (48X)
A1 CORNER
SIDE VIEW
1.10 0.10
SEATING PLANE 0.21 0.05
0.15
48ba TFBGA.BK8x10-ILL.7
Note:
1. Complies with the general requirements of JEDEC publication 95 MO-210, although some dimensions may be more stringent. (This specific outline variant has not yet been registered) 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm.
48-BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) 8MM X 10MM SST PACKAGE CODE: BK
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 2000 Silicon Storage Technology, Inc.
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